A Family of Accelerators for Matrix-Vector Arithmetics Based on High-Radix Multiplier Structures

A methodology for designing processor architectures oriented to matrix-vector operations is proposed in this paper. The methodology is based on high-radix multiplication where first a list of potential partial products (PPs) of one operand with all possible t-bit numbers (t ∈ {2, 3, 4}) are computed by simple shifts and additions, then selected PPs from this list are shifted and added according to t-bit slices of the other operand. Main advantage of the proposed method is that the list of potential PPs may be reused whenever one multiplicand is to be multiplied with several multipliers. Another advantage is that the hardware blocks involved for high-radix multiplication may also be used independently to implement other tasks such as parallel addition/subtractions, accumulations. This allows introducing a group of modifications to high-radix multiplier structures making them reconfigurable so that single devices having two-fold functionalities of either programmable processors or reconfigurable hardware accelerators may be designed.